Integrated circuit (IC) packaging is a step closer to the final stage of semiconductor device fabrication, followed by IC testing. An individual die, which represents the core of the device, is encased in a support that prevents physical damage and corrosion, and supports the electrical contacts required to assemble the IC into a system. IC packaging generally comprises the steps or the technology of mounting and interconnecting devices. The earliest integrated circuits were packaged in ceramic flat packs. Other current packaging technologies include ball grid array (BGA) packages, flip-chip packages, and many more. When multiple dies are stacked in one package, it is called a system in package (SiP), or a three-dimensional circuit.
An IC may comprise transistors formed on a substrate. An interconnect structure, which includes metal lines and vias may be formed therein to connect transistors and devices. Metal pads may be formed over the interconnect structure. Additional packaging metal interconnects such as under-bump-metallurgy (UBM) layers, post passivation interconnects, and redistribution layers may be formed in the packaging process over the metal pads. Various polymer layers may be formed to separate and support the metal interconnects in the packages.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.